The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Dec. 19, 2019
Applicant:

Omnivision Technologies, Inc., Santa Clara, CA (US);

Inventors:

Kazufumi Watanabe, Mountain View, CA (US);

Chih-Wei Hsiung, San Jose, CA (US);

Vincent Venezia, Los Gatos, CA (US);

Young Woo Jung, San Jose, CA (US);

Geunsook Park, Cupertino, CA (US);

Lindsay Alexander Grant, Campbel, CA (US);

Assignee:

OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14605 (2013.01); H01L 27/14612 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14687 (2013.01);
Abstract

Backside illuminated sensor pixel structure. In one embodiment, and image sensor includes a plurality of pixels arranged in rows and columns of a pixel array that are disposed in a semiconductor substrate. Individual photodiodes of the pixel array are configured to receive an incoming light through a backside of the semiconductor substrate. A front side of the semiconductor substrate is opposite from the backside. A plurality of transistors disposed proximate to the front side of the semiconductor substrate, are arranged in a row along an outer perimeter of the photodiodes of the respective pixel; and a plurality of isolation structures arranged to bracket the row of transistors along the outer perimeter of the photodiodes. A plurality of contacts electrically contacting the plurality of isolation structures, and the contacts are configured to voltage-bias the plurality of isolation structures.


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