The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Apr. 13, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eunyeoung Choi, Hwaseong-si, KR;

Suhyeong Lee, Suwon-si, KR;

Yohan Lee, Seoul, KR;

Yongseok Cho, Yeongcheon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/42324 (2013.01);
Abstract

An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.


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