The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2022
Filed:
Aug. 27, 2020
Applicant:
Kioxia Corporation, Tokyo, JP;
Inventor:
Soichi Homma, Yokkaichi Mie, JP;
Assignee:
KIOXIA CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 24/92 (2013.01); H01L 21/563 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 25/18 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/11831 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/11912 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13582 (2013.01); H01L 2224/13611 (2013.01); H01L 2224/13639 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/27831 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33106 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/8392 (2013.01); H01L 2224/83191 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92143 (2013.01);
Abstract
A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.