The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2022
Filed:
May. 27, 2019
Daicel Corporation, Osaka, JP;
Naoko Tsuji, Tokyo, JP;
DAICEL CORPORATION, Osaka, JP;
Abstract
Provided is a method for manufacturing a semiconductor device suitable for achieving low wiring resistance between semiconductor elements that is bonded via an adhesive layer and multi-layered. The method according to the present invention is as follows. First, a wafer laminate (W) is prepared, the wafer laminate (W) including a wafer () having a circuit forming surface (), a wafer () having a main surface () and a back surface (), and an adhesive layer () containing an SiOC-based polymer. Then, a hole (H) is formed in the wafer laminate (W) by etching the wafer laminate (W) from the wafer () side via a mask pattern masking a portion of the main surface () side of the wafer (), the hole (H) extending through the wafer () and the adhesive layer () and reaching a wiring pattern () in the wafer (). Then, an insulating film () is formed on an inner surface of the hole (H). Then, the insulating film () on a bottom surface of the hole (H) is removed. Then, the wafer laminate (W) is subjected to a cleaning treatment (an oxygen plasma treatment and/or an Ar sputtering treatment). Then, a conductive portion is formed in the hole (H).