The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jun. 04, 2021
Applicant:

Realtek Semiconductor Corp., HsinChu, TW;

Inventors:

Chia-Jung Chang, HsinChu, TW;

Chiu-Yun Tsai, HsinChu, TW;

Fu-Ching Hsu, HsinChu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G11C 11/4093 (2006.01); G11C 29/36 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 11/4093 (2013.01); G11C 29/36 (2013.01); G11C 29/4401 (2013.01);
Abstract

A data access system includes a flash memory, a first inversion circuit, a block buffer memory, an error checking and correcting circuit, a second inversion circuit, and an application circuit. The first inversion circuit inverts a plurality of pieces of data stored in a block of the flash memory to generate a plurality of pieces of inverted data. The block buffer memory stores the plurality of pieces of inverted data. When the ECC circuit determines that the plurality of pieces of inverted data are correctable, the ECC circuit corrects at least one piece of inverted data stored in the block buffer memory. The second inversion circuit inverts the plurality of pieces of inverted data stored in the block buffer memory to generate a plurality of pieces of recovered data. The application circuit receives the plurality of pieces of recovered data and performs a corresponding operation accordingly.


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