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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11501834 B1

PDFFull Text
Date of Patent:
Nov. 15, 2022

Filed:

Feb. 22, 2021

Semiconductor memory system including first and second semiconductor memory chips and a common signal line

Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Noboru Shibata, Kawasaki, JP;

Hiroshi Sukegawa, Minato-ku, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Hoai V Ho

Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 16/30 (2013.01);
Abstract

A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Find Patent Forward Citations

Shibata, Noboru. (2022). Semiconductor memory system including first and second semiconductor memory chips and a common signal line (U.S. Patent No. 11501834). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11501834

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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