The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jun. 17, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Kosuke Hatsuda, Bunkyo Tokyo, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 7/106 (2013.01); G11C 11/1659 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01);
Abstract

In a memory, a first node holds first data from a first cell. A second node holds second data from a second cell near the first cell. A differential circuit includes a first current path passing a first current corresponding to a voltage of the first node and a second current path passing a second current corresponding to a voltage of the second node, and outputs an output signal corresponding to a voltage difference between the first and the second nodes from an output part. A first register latches the output signal and output the signal as a hold signal. A first offset part is connected to the first current path and offsets the first current when the hold signal has a first logic level. A second offset part is connected to the second current path and offsets the second current when the hold signal has a second logic level.


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