Contention-adapted read-write pulse generation circuitry

Abstract

Various implementations described herein refer to a device having an address bus that provides multi-port addresses from multiple ports including a first address from a first port and a second address from a second port. The device may have column contention-detection circuitry that receives the multi-port addresses from the address bus, compares the first address from the first port with the second address from the second port and provides a contention adjustment signal based on the comparison between the first address and the second address. The device may have bitline collision circuitry that receives the contention adjustment signal, senses wire-to-wire variation related to bitline coupling effects and provides a bitline collision signal based on sensing the bitline coupling effects.