The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jun. 01, 2021
Applicant:

Netlist Inc., Irvine, CA (US);

Inventors:

Jordan Horwich, Corona, CA (US);

Jerry Alston, Coto de Caza, CA (US);

Chih-Cheh Chen, Ladera Ranch, CA (US);

Patrick Lee, Irvine, CA (US);

Scott Milton, Irvine, CA (US);

Jeekyoung Park, Irvine, CA (US);

Assignee:

Netlist, Inc., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 12/0862 (2016.01); G06F 12/0891 (2016.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 12/0862 (2013.01); G06F 12/0891 (2013.01); G06F 13/1642 (2013.01);
Abstract

A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.


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