The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

May. 27, 2020
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Daniel L. Helmick, Broomfield, CO (US);

Liam Parker, Edinburgh, GB;

Alan D. Bennett, Edinburgh, GB;

Peter Grayson, Grand Rapids, MI (US);

Sergey Anatolievich Gorobets, Edinburgh, GB;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G06F 9/30 (2018.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1096 (2013.01); G06F 9/30029 (2013.01); G06F 11/1068 (2013.01); G06F 12/0246 (2013.01); G06F 13/1673 (2013.01); G06F 2212/7204 (2013.01);
Abstract

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second zone is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second zone. The updated second XOR data is copied from the RAM1 to the RAM2.


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