The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jun. 04, 2021
Applicant:

Huawei Technologies Co., Ltd., Guangdong, CN;

Inventors:

Jianbo Xiang, Hangzhou, CN;

Bo Zhang, Hangzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/445 (2018.01); G06F 8/61 (2018.01); G06F 8/65 (2018.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 9/44505 (2013.01); G06F 8/62 (2013.01); G06F 8/65 (2013.01); G06F 11/3027 (2013.01); G06F 11/3055 (2013.01); G06F 11/349 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

An FPGA upgrade method is provided, including: delivering, by a host, an upgrade instruction to an FPGA; uninstalling a PCIe driver corresponding to the FPGA to let a status of the PCIe link be changed to link down; continuously monitoring, in a first expiration time, whether the status of the PCIe link is changed to link up; and if yes, reloading the PCIe driver. The method further includes: after the FPGA receives the upgrade instruction, continuously monitoring, in a second expiration time, whether the status of the PCIe link is changed to link down, if yes, loading the configuration data from the FPGA configuration memory for upgrade; and after upgrade is completed, negotiating, by the FPGA, with the host to restore the status of the PCIe link to link up that is used for reloading the PCIe driver upon detection by the host.


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