The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2022
Filed:
Jan. 17, 2020
Qualcomm Technologies, Inc., San Diego, CA (US);
Muthu M. Baskaran, Old Tappan, NJ (US);
Thomas Henretty, Brooklyn, NY (US);
Ann Johnson, Saratoga, CA (US);
Athanasios Konstantinidis, Brooklyn, NY (US);
M. H. Langston, Beacon, NY (US);
Janice O. McMahon, Bethesda, MD (US);
Benoit J. Meister, New York, NY (US);
Paul D. Mountcastle, Moorestown, NJ (US);
Aale Naqvi, New York, NY (US);
Benoit Pradelle, Cologne, DE;
Tahina Ramananandro, New York, NY (US);
Sanket Tavarageri, New York, NY (US);
Richard A. Lethin, New York, NY (US);
Reservoir Labs Inc., San Diego, CA (US);
Abstract
A compilation system using an energy model based on a set of generic and practical hardware and software parameters is presented. The model can represent the major trends in energy consumption spanning potential hardware configurations using only parameters available at compilation time. Experimental verification indicates that the model is nimble yet sufficiently precise, allowing efficient selection of one or more parameters of a target computing system so as to minimize power/energy consumption of a program while achieving other performance related goals. A voltage and/or frequency optimization and selection is presented which can determine an efficient dynamic hardware configuration schedule at compilation time. In various embodiments, the configuration schedule is chosen based on its predicted effect on energy consumption. A concurrency throttling technique based on the energy model can exploit the power-gating features exposed by the target computing system to increase the energy efficiency of programs.