The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jan. 04, 2021
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

John B. Bowlerwell, Edinburgh, GB;

Andrew J. Howlett, Edinburgh, GB;

Graeme S. Angus, Edinburgh, GB;

Andrei Dumitriu, Edinburgh, GB;

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/563 (2006.01); G05F 1/575 (2006.01); G05F 1/62 (2006.01); H03K 17/00 (2006.01); H04R 3/00 (2006.01);
U.S. Cl.
CPC ...
G05F 1/563 (2013.01); G05F 1/575 (2013.01); G05F 1/62 (2013.01); H03K 17/002 (2013.01); H04R 3/00 (2013.01);
Abstract

The present disclosure relates to circuitry for selecting a bias voltage to output at a bias voltage output node of the circuitry. The circuitry comprises a first circuit node configured to receive a first voltage from a first, unregulated, voltage source and a second circuit node configured to receive a second voltage from a second, regulated, voltage source. A switch arrangement configured to selectively couple the bias voltage output node to the first circuit node or the second circuit node is also provided.


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