The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

Aug. 14, 2020
Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventors:

Masao Kondo, Nagaokakyo, JP;

Kenji Sasaki, Nagaokakyo, JP;

Shigeki Koya, Nagaokakyo, JP;

Shinnosuke Takahashi, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H03F 1/56 (2006.01); H03F 3/20 (2006.01);
U.S. Cl.
CPC ...
H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/13013 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/10337 (2013.01); H01L 2924/13051 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19103 (2013.01); H01L 2924/30101 (2013.01); H01L 2924/30107 (2013.01); H03F 1/56 (2013.01); H03F 3/20 (2013.01); H03F 2200/222 (2013.01); H03F 2200/318 (2013.01); H03F 2200/387 (2013.01);
Abstract

Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.


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