Neural network computation circuit including semiconductor memory element, and method of operation

Abstract

Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.