The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

May. 13, 2021
Applicant:

Palo Alto Research Center Incorporated, Palo Alto, CA (US);

Inventors:

Aleksandar B. Feldman, Santa Cruz, CA (US);

Johan de Kleer, Los Altos, CA (US);

Alexandre Campos Perez, San Mateo, CA (US);

Ion Matei, Mountain View, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G01R 31/00 (2006.01); G01R 31/28 (2006.01); G01R 31/3183 (2006.01); G01R 31/3181 (2006.01); G06F 30/3323 (2020.01); G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G01R 31/31813 (2013.01); G01R 31/31835 (2013.01); G01R 31/318307 (2013.01); G01R 31/318357 (2013.01); G01R 31/318371 (2013.01); G06F 30/30 (2020.01); G06F 30/3323 (2020.01); G06F 30/398 (2020.01); G01R 31/28 (2013.01); G06F 11/00 (2013.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01);
Abstract

One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.


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