The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

Sep. 09, 2020
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Abhay Kumar Jain, Palo Alto, CA (US);

Richard P. Spillane, Palo Alto, CA (US);

Wenguang Wang, Palo Alto, CA (US);

Nitin Rastogi, Palo Alto, CA (US);

Mounesh Badiger, Bangalore, IN;

Assignee:

VMWARE, INC., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/02 (2006.01); G06F 12/0871 (2016.01); G06F 12/084 (2016.01); G06F 9/50 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 12/0238 (2013.01); G06F 9/5016 (2013.01); G06F 9/5022 (2013.01); G06F 12/084 (2013.01); G06F 12/0871 (2013.01); G06F 9/5077 (2013.01); G06F 2009/45583 (2013.01); G06F 2209/508 (2013.01); G06F 2209/5011 (2013.01);
Abstract

An example method of memory management in a computing system having a plurality of processors includes: receiving a first memory allocation request at a memory manager from a process executing on a processor of the plurality of processors in the computing system; allocating a local memory pool for the processor from a global memory pool for the plurality of processors in response to the first memory allocation request; and allocating memory from the local memory pool for the processor in response to the first memory allocation request without locking the local memory pool.


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