The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Dec. 15, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Sung Lae Oh, Cheongju-si, KR;

Dong Hyuk Kim, Seoul, KR;

Tae Sung Park, Icheon-si, KR;

Soo Nam Jung, Seoul, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 27/11526 (2017.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 27/11573 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08147 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.


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