The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Dec. 02, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyeon Gyu You, Hwaseong-si, KR;

Ji Su Yu, Seoul, KR;

Jae-Ho Park, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/5286 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/41733 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a first cell region and a filler region that are adjacent each other in a first direction. The semiconductor device includes an active pattern extending in the first direction, inside the first cell region, a gate electrode extending in a second direction intersecting the first direction, on the active pattern, a gate contact electrically connected to an upper surface of the gate electrode, a source/drain contact electrically connected to a source/drain region of the active pattern, adjacent a side of the gate electrode, a connection wiring that extends in the first direction over the first cell region and the filler region, and is electrically connected to one of the gate contact or the source/drain contact, and a filler wiring that is inside the filler region. A related layout design method and fabricating method are also provided.


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