The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Mar. 25, 2021
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Chin-Wei Lin, San Jose, CA (US);

Shinya Ono, Santa Clara, CA (US);

Gihoon Choo, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 2310/061 (2013.01); G09G 2330/028 (2013.01); G09G 2330/08 (2013.01);
Abstract

A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit may include a scan driver circuit and a scan inverter circuit. An enable transistor may be interposed between the scan driver circuit and the scan inverter circuit and may be selectively disabled to decouple the scan inverter circuit from the scan driver circuit to allow the scan inverter circuit to operate independent from the scan driver circuit. The scan inverter circuit may include a transistor that receives a scan pulse signal from the scan driver circuit and may further include additional transistors connected in a negative feedback configuration to reduce a drain-to-source voltage across the transistor to reduce leakage across the transistor during blanking times.


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