The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Mar. 31, 2017
Applicant:

Telefonaktiebolaget Lm Ericsson (Publ), Stockholm, SE;

Inventors:

Mozhgan Mahloo, Solna, SE;

Amir Roozbeh, Kista, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 9/50 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 9/5077 (2013.01); G06F 11/301 (2013.01); G06F 11/3006 (2013.01); G06F 11/3048 (2013.01); G06F 11/3051 (2013.01); G06F 11/3055 (2013.01); G06F 11/3096 (2013.01); G06F 11/3423 (2013.01); G06F 11/3428 (2013.01); G06F 11/3433 (2013.01); G06F 11/3442 (2013.01); G06F 11/3495 (2013.01); G06F 2009/45583 (2013.01); G06F 2201/815 (2013.01); G06F 2201/86 (2013.01); G06F 2201/88 (2013.01); G06F 2201/885 (2013.01); G06F 2209/501 (2013.01); G06F 2209/5011 (2013.01);
Abstract

A performance manager () and a method () performed thereby are provided, for managing the performance of a logical server of a data center. The data center comprises at least one memory pool in which a memory block has been allocated to the logical server. The method () comprises determining () performance characteristics associated with a first portion of the memory block, comprised in a first memory unit of the at least one memory pool; and identifying () a second portion of the memory block, comprised in a second memory unit of the at least one memory pool, to which data of the first portion of the memory block may be migrated to apply performance characteristics associated with the second portion. The method () further comprises initiating migration () of the data to the second portion of the memory block.


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