The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Jul. 01, 2021
Applicant:

Datadirect Network, Inc., Chatsworth, CA (US);

Inventors:

Zhiwei Sun, Columbia, MD (US);

Yuhua Guo, Columbia, MD (US);

Jason Micah Cope, Highland, MD (US);

Eric Barton, Bristol, GB;

Assignee:

DATADIRECT NETWORKS INC., Chatsworth, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0804 (2016.01); G06F 16/22 (2019.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/068 (2013.01); G06F 3/0644 (2013.01); G06F 3/0647 (2013.01); G06F 3/0659 (2013.01); G06F 12/0804 (2013.01); G06F 16/2246 (2019.01); G06F 2212/1024 (2013.01); G06F 2212/608 (2013.01);
Abstract

A system and method for efficiently storing and accessing large volumes of metadata persistent on Non-Volatile Memory (NVM) storage systems is provided. The system applies log-structured, Copy-on-Write (CoW) Btree methods, and supports a core-affine data and resource partitioning approaches on the system's architecture and platform with a high-degree of parallelism within the CPU, NVMe storage, and networking devices. The subject system and method efficiently indexes both in-core (DRAM resident) and out-of-core (NVM resident) metadata, supports a variety of data access patterns, supports CoW features and provides verifiable data safety and integrity capabilities. The present system minimizes latencies over all aspects of the metadata management and access path by leveraging core-affine resource partitioning with runtime environment providing lightweight user-level threads with low-latency context switching that execute within the exclusive context of a dedicated CPU core, and partitioned resources.


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