The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2022
Filed:
Jul. 02, 2019
Nvidia Corporation, Santa Clara, CA (US);
Aniket Naik, Fremont, CA (US);
Tezaswi Raja, San Jose, CA (US);
Kevin Wilder, Menlo Park, CA (US);
Rajeshwaran Selvanesan, Cupertino, CA (US);
Divya Ramakrishnan, San Jose, CA (US);
Daniel Rodriguez, Dublin, CA (US);
Benjamin Faulkner, San Jose, CA (US);
Raj Jayakar, San Jose, CA (US);
Fei (Walter) Li, Milpitas, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.