The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Jan. 27, 2021
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics (Shenzhen) R&d Co. Ltd, Nanshan, CN;

Inventors:

Ignazio Pisello, Tremestrieri Etneo, IT;

Yu Yong Wang, GuangDong, CN;

Dario Arena, Messina, IT;

Qi Yu Liu, Nanshan, CN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G06F 1/06 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318533 (2013.01); G01R 31/318536 (2013.01); G01R 31/318538 (2013.01); G01R 31/318541 (2013.01); G01R 31/318552 (2013.01); G01R 31/318572 (2013.01); G01R 31/31713 (2013.01); G01R 31/31727 (2013.01); G06F 1/06 (2013.01);
Abstract

A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.


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