The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Jan. 20, 2020
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Andrea Barbieri, Casalpusterlengo, IT;

Aldo Vidoni, Milan, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/52 (2006.01); B06B 1/02 (2006.01); B06B 1/06 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
B06B 1/0223 (2013.01); B06B 1/06 (2013.01); H03F 3/45475 (2013.01); H03H 11/52 (2013.01); H03F 2200/129 (2013.01); H03F 2200/156 (2013.01); H03F 2203/45116 (2013.01);
Abstract

A negative impedance circuit includes: a differential circuit stage; a positive feedback path from an output of the differential circuit stage to a first input of the differential circuit stage; and a negative feedback path from the output of the differential circuit stage to a second input of the differential circuit stage. The negative feedback path includes a first transistor, and a unitary gain path from the output of the differential circuit stage to the second input of the differential circuit stage, the unitary gain path coupled to ground via a reference impedance. The positive feedback path includes a second transistor. The first and second transistors are coupled in a current mirror arrangement and have respective control electrodes configured to be driven by the output of the differential circuit stage, where the negative impedance circuit causes a negative impedance at the first input of the differential circuit stage.


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