The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2022

Filed:

Jun. 04, 2021
Applicant:

Omnivision Technologies, Inc., Santa Clara, CA (US);

Inventors:

Wei Deng, Sunnyvale, CA (US);

Tomoyasu Tate, Cupertino, CA (US);

Rui Wang, San Jose, CA (US);

Assignee:

OmniVision Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/369 (2011.01); H04N 5/347 (2011.01); H04N 5/351 (2011.01); H04N 5/378 (2011.01); H04N 5/374 (2011.01); H04N 9/04 (2006.01); H01L 27/146 (2006.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H04N 5/36961 (2018.08); H04N 5/347 (2013.01); H04N 5/351 (2013.01); H04N 5/378 (2013.01); H04N 5/3745 (2013.01); H04N 9/0455 (2018.08);
Abstract

An imaging device includes a pixel array including pixel circuits arranged into rows and columns. Each bitline of a plurality of bitlines is coupled to a respective column of pixel circuits of the pixel array. The plurality of bitlines is grouped into pairs of bitlines. A plurality of binning circuits is coupled to the plurality of bitlines. Each binning circuit is coupled to a respective pair of bitlines and is responsive to a multi-mode select signal. Each binning circuit is configured to output a binned signal responsive to the first and second bitlines of the respective bitline pair in a first mode. Each binning circuit is configured to output a first signal from a first bitline of the respective bitline pair in a second mode. Each binning circuit is configured to output a second signal from the second bitline of the respective bitline pair in a third mode.


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