The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2022

Filed:

Nov. 11, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventor:

Xiaobao Wang, Cupertino, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/20 (2006.01); G11C 7/00 (2006.01); G11C 7/22 (2006.01); G11C 7/04 (2006.01); G06F 1/04 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 7/222 (2013.01); G11C 7/1093 (2013.01); G11C 2207/2254 (2013.01);
Abstract

Examples herein relate to devices that include a strobe tree circuit for capturing data using a memory-sourced strobe. In an example, a device includes a data capture path including first and second flip-flops, and a strobe tree including a comparator and first and second multiplexers. The comparator is configured to output complementary signals on first and second output nodes. First and second selection input nodes of the first multiplexer are connected to the first and second output nodes of the comparator, respectively. First and second selection input nodes of the second multiplexer are connected to the second and first output nodes of the comparator, respectively. The read strobe tree is configured to provide first and second signals output from the first and second multiplexers to first and second nodes, respectively. Clock input nodes of the first and second flip-flops are connected to the first and second nodes, respectively.


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