The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2022

Filed:

Dec. 23, 2019
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Kazutaka Ikegami, Tokyo, JP;

Shinobu Fujita, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G06F 7/38 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
G06F 7/383 (2013.01); G11C 11/161 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1675 (2013.01); G11C 11/1655 (2013.01); G11C 11/1673 (2013.01); H01L 27/228 (2013.01);
Abstract

According to one embodiment, an arithmetic device includes a first computational circuit including a first string, the first string having a first magnetoresistive effect element on a first conducting layer; a second computational circuit including a second strings, the second string having second magnetoresistive effect element on a second conducting layer; a third computational circuit executing computational processing using a first signal from the first computational circuit and a second signal from the second computational circuit; and a control circuit. The control circuit sets a condition on write operations with respect to at least one of the first and second magnetoresistive effect elements, based on information related to write error in at least one of the first and second magnetoresistive effect elements.


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