The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2022

Filed:

Apr. 01, 2020
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Vishwas Saxena, Karnataka, IN;

Lalit Mohan Soni, Karnataka, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 16/13 (2019.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0611 (2013.01); G06F 3/0679 (2013.01); G06F 12/06 (2013.01); G06F 16/13 (2019.01); G06F 2212/7202 (2013.01);
Abstract

Aspects of a storage device are provided which reduce write amplification by minimizing data flushes from cache to SLC blocks during RMW operations. A memory of the storage device includes a first memory location of one or more single-level cells and a second memory location of one or more multiple-level cells. A controller of the storage device receives first data associated with a first range of logical addresses and second data associated with a second range of logical addresses. During a RMW operation of the first data, the controller determines whether the first range overlaps with the second range, and stores or flushes the second data in the first memory location when an overlap is determined. The controller stores or writes the second data in the second memory location when an overlap is not determined. Accordingly, data flushing to the single-level cells is minimized when no overlap is determined.


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