The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Sep. 26, 2017
Applicant:

Zte Corporation, Shenzhen, CN;

Inventor:

Gregory Mirsky, Pleasanton, CA (US);

Assignee:

ZTE Corporation, Guangdong, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 43/0852 (2022.01); H04L 43/106 (2022.01); H04L 45/50 (2022.01); H04L 45/00 (2022.01); H04L 43/12 (2022.01); H04L 43/50 (2022.01);
U.S. Cl.
CPC ...
H04L 43/0852 (2013.01); H04L 43/106 (2013.01); H04L 43/12 (2013.01); H04L 43/50 (2013.01); H04L 45/22 (2013.01); H04L 45/26 (2013.01); H04L 45/50 (2013.01);
Abstract

Residence time is a variable part of the propagation delay of the packet. Information about the propagation delay for each transient node can be used as performance metric to calculate the Traffic Engineered route that can conform to delay and delay variation requirements. In an exemplary embodiment, a computing device uses special test packets to measure residence time. The computing device calculates routes to direct special test packets to one or more nodes. A node may calculate the residence time metric, such as a residence time variation (RTV), or residence time (RT) per ordered set of ingress and egress interfaces of the node. The computing device may also collect the residence time metric per test set from each node and may use this information to calculate the Test Engineered route.


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