The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Oct. 16, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Rahul Sharma, Bangalore, IN;

Aswath Vs, Kerala, IN;

Sriram Murali, Karnataka, IN;

Prasad Gandewar, Bangalore, IN;

Sandeep Kesrimal Oswal, Karnataka, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H04L 1/00 (2006.01); H04W 88/08 (2009.01);
U.S. Cl.
CPC ...
H03M 1/0607 (2013.01); H04L 1/0071 (2013.01); H04W 88/08 (2013.01);
Abstract

Analog gain correction circuitry and analog switching clock edge timing correction circuitry can provide coarse correction of interleaving errors in radio-frequency digital-to-analog converters (RF DACs), such as may be used in 5G wireless base stations. The analog correction can be supplemented by digital circuitry configured to 'pre-cancel' an interleaving image by adding to a digital DAC input signal a signal equal and opposite to an interleaving image created by the interleaving DAC, such that the interleaving image is effectively mitigated. Error correction control parameters can be periodically adjusted for changes in temperature by a controller coupled to an on-chip temperature sensor. A model useful for understanding the sources of error in interleaving DACs is also described.


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