The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Jul. 09, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Inhak Lee, Seoul, KR;

Seunghun Lee, Hwaseong-si, KR;

Sangyeop Baeck, Yongin-si, KR;

Seunghan Park, Gunpo-si, KR;

Hyejin Lee, Osan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 27/11 (2006.01); G11C 11/417 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); G11C 5/063 (2013.01); G11C 11/412 (2013.01); G11C 11/417 (2013.01);
Abstract

An integrated circuit includes: a first wiring layer on which a first bit line pattern and a positive power supply pattern, a first power supply line landing pad, and a first word line landing pad are formed; a second wiring layer on which a first negative power supply pattern connected to the first power supply line landing pad, and a first word line pattern connected to the first word line landing pad are formed; a third wiring layer on which a second negative power supply pattern connected to the first negative power supply pattern, and a second word line landing pad connected to the first word line pattern are formed; and a fourth wiring layer on which a second word line pattern, connected to the second word line landing pad, are formed.


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