The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2022
Filed:
Jan. 13, 2021
Arm Limited, Cambridge, GB;
Olivier Dominique Rizzo, Roquebrune sur Argens, FR;
Grégorie Martin, Valbonne, FR;
Stephane Cauneau, Gofe-Juan, FR;
Yannis Jallamion-Grive, Mouans Sartoux, FR;
Arm Limited, Cambridge, GB;
Abstract
A computer-implemented method for designing a floorplan for an integrated circuit includes determining a circuit design for the integrated circuit, wherein the circuit design for the integrated circuit has a system device and a logic device. Logical definitions for the system device and the logic device are determined. A plurality of interconnect devices are determined. A plurality of interconnect figures of merit (FOMs) associated with the plurality of interconnect devices are also determined. The method includes determining, with an optimization operation, a candidate floorplan for the circuit design based upon the logical definitions for the system device, the logic device, the plurality of interconnect devices, and the interconnect FOMs for the interconnect devices. The candidate floorplan is determined based upon parameters associated with computational performance, power consumption, and physical area of the candidate floorplan for the circuit design. The candidate floorplan is implemented as the integrated circuit.