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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11475195 B1

PDFFull Text
Date of Patent:
Oct. 18, 2022

Filed:

Jan. 25, 2021

Computer-implemented method and computing system for designing integrated circuit by considering timing delay

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jong-pil Lee, Suwon-si, KR;

Bong-il Park, Seongnam-si, KR;

Moon-su Kim, Gimpo-si, KR;

Sun-ik Heo, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Sughrue Mion, PLLC

Primary Examiner:

Suresh Memula

Int. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 30/3312 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/3312 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01);
Abstract

A method includes performing, using a processor, a synthesis operation to generate a netlist from input data about an integrated circuit, placing and routing, using the one processor, standard cells defining the integrated circuit using the netlist, to generate layout data and wire data, extracting, using the processor, parasitic components from the layout data, and performing, using the processor, timing analysis of the integrated circuit according to timing constraints, based on the layout data and the wire data.

Find Patent Forward Citations

Lee, Jong-pil. (2022). Computer-implemented method and computing system for designing integrated circuit by considering timing delay (U.S. Patent No. 11475195). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11475195

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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