The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Aug. 26, 2021
Applicants:

Kohei Sakurai, Atsugi, JP;

Shinichiro Maki, Hiratsuka, JP;

Inventors:

Kohei Sakurai, Atsugi, JP;

Shinichiro Maki, Hiratsuka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01); G05F 3/02 (2006.01); G01R 31/52 (2020.01); H03K 3/037 (2006.01); G05F 1/56 (2006.01); G01R 19/165 (2006.01); H03K 5/24 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/52 (2020.01); G01R 19/16576 (2013.01); G05F 1/56 (2013.01); H03K 3/037 (2013.01); H03K 5/24 (2013.01); H03K 2005/00013 (2013.01);
Abstract

A power supply semiconductor integrated circuit includes an output transistor, a control circuit, a first-fault detection circuit, a second-fault detection circuit, a delay circuit, and a latch circuit. The output transistor is connected between a voltage-input terminal to which a DC voltage is input and a voltage-output terminal. The control circuit controls the output transistor. The first-fault detection circuit detects a first fault. The second-fault detection circuit detects a second fault different from the first fault. The delay circuit delays an output of the first-fault detection circuit and an output of the second-fault detection circuit. The latch circuit captures and holds an output of the delay circuit. The delay circuit includes: a constant current source for charging a delay capacitor; a discharge switch for discharging the delay capacitor; and a voltage comparator circuit that compares a charge voltage across the delay capacitor and a predetermined voltage.


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