The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Nov. 16, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Miao Li, San Diego, CA (US);

Li Sun, Irvine, CA (US);

Hao Liu, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); H03G 5/16 (2006.01); H03G 3/30 (2006.01); H03F 1/30 (2006.01);
U.S. Cl.
CPC ...
H03G 5/165 (2013.01); H03F 3/04 (2013.01); H03G 3/30 (2013.01); H03F 1/302 (2013.01); H03G 2201/103 (2013.01);
Abstract

A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.


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