The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Apr. 06, 2020
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Mohammed T. Quddus, Chandler, AZ (US);

Mihir Mudholkar, Phoenix, AZ (US);

Ali Salih, Mesa, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/872 (2006.01); H01L 21/762 (2006.01); H01L 29/812 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66613 (2013.01); H01L 21/76205 (2013.01); H01L 29/4236 (2013.01); H01L 29/8128 (2013.01); H01L 29/8725 (2013.01);
Abstract

A semiconductor device structure comprises a region of semiconductor material comprising a first conductivity type, a first major surface, and a second major surface opposite to the first major surface. A first trench gate structure includes a first trench extending from the first major surface into the region of semiconductor material, a first dielectric structure is over sidewall surfaces and a portion of a lower surface of the first trench, wherein the first dielectric structure comprises a first opening adjacent to the lower surface of the first trench, a first recessed contact extends through the first opening, and a first contact region is over the first recessed contact within the first trench, wherein the first recessed contact and the first contact region comprise different materials. A first doped region comprising a second dopant conductivity type opposite to the first conductivity type is in the region of semiconductor material and is spaced apart from the first major surface and below the first trench. A gate contact region is in the region of semiconductor material and is electrically connected to the first doped region.


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