The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Jun. 25, 2020
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Chih-Wei Huang, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 27/108 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5329 (2013.01); H01L 21/7682 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10855 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01);
Abstract

The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad.


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