The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Jul. 06, 2020
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Kazuhito Tanaka, Shiga, JP;

Masaki Maeda, Hiroshima, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/36 (2006.01); G11C 29/10 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 29/10 (2013.01); G11C 29/36 (2013.01); G11C 29/44 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit.


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