The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Mar. 10, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Harish Singidi, Fremont, CA (US);

Amiya Banerjee, Bangalore, IN;

Shantanu Gupta, Freemont, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 7/10 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps.


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