The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Jun. 11, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Kazuki Okawa, Yokohama, JP;

Hiroyuki Hara, Fujisawa, JP;

Atsushi Kawasumi, Fujisawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); H03K 19/173 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 5/06 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); H03K 19/1737 (2013.01);
Abstract

Provided is a semiconductor storage device including: a substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction; a plurality of first region memory cells provided in a plurality of layers provided parallel to the substrate surface and in a third direction, the first region memory cells being provided above a rectangular shaped first region provided on the substrate surface, the first region having a first side parallel to the first direction and a second side parallel to the second direction when viewed from the third direction intersecting the first direction and the second direction; a plurality of first region wirings provided between the first region memory cells; a plurality of second region memory cells provided in the layers, the second region memory cells being provided above a rectangular shaped second region having a third side parallel to the first direction and a fourth side parallel to the second direction when viewed from the third direction; a plurality of second region wirings provided between the second region memory cells; and a control circuit capable of executing a reading operation.


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