The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2022
Filed:
Mar. 05, 2021
Applicant:
Arm Limited, Cambridge, GB;
Inventors:
Akash Bangalore Srinivasa, Bangalore, IN;
Andy Wangkun Chen, Austin, TX (US);
Penaka Phani Goberu, Bangalore, IN;
Yew Keong Chong, Austin, TX (US);
Assignee:
Arm Limited, Cambridge, GB;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4074 (2006.01); G11C 5/06 (2006.01); G11C 11/4093 (2006.01); G11C 5/14 (2006.01); G11C 11/4094 (2006.01); G11C 11/4076 (2006.01); H03K 19/017 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 5/063 (2013.01); G11C 5/14 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); H03K 19/01742 (2013.01);
Abstract
Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.