The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Jan. 29, 2021
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Bernard Deadman, Austin, TX (US);

Michael Allen, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06N 3/08 (2006.01); G06F 11/22 (2006.01); G06F 11/10 (2006.01); G06F 9/345 (2018.01); G06F 11/27 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/30101 (2013.01); G06F 9/30134 (2013.01); G06F 9/345 (2013.01); G06F 11/1004 (2013.01); G06F 11/22 (2013.01); G06F 11/27 (2013.01); G06N 3/08 (2013.01);
Abstract

A processor is described that includes a plurality of compute units. One or more test pattern generators generates one or more test patterns and inputs the one or more test patterns into one or more of the plurality of compute units during testing, which testing includes processing of the one or more test patterns by one or more of the plurality of compute units. One or more control and sequencing logic units identifies an idle period during normal use of the processor in which a compute unit of the plurality of compute units is idle. The one or more control and sequencing units controls the test pattern generator to generate and input the one or more test patterns to the idle compute unit and controls the compute unit to process the one or more test patterns during the idle period. One or more comparators compares a result of testing with an expected result of testing to determine if the compute unit is functioning correctly.


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