The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

May. 29, 2019
Applicant:

Phison Electronics Corp., Miaoli, TW;

Inventors:

Chieh Yang, Taipei, TW;

Yi-Hsuan Lin, New Taipei, TW;

Tai-Yuan Huang, New Taipei, TW;

Ping-Chuan Lin, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0652 (2013.01); G06F 3/0608 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G06F 12/023 (2013.01); G06F 12/0253 (2013.01);
Abstract

A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold.


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Yang, Chieh. (2022). Data writing method using different programming modes based on the number of available physical erasing units, memory control circuit unit and memory storage device (U.S. Patent No. 11467758). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11467758

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