The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Feb. 22, 2021
Applicant:

Mitsubishi Electric Research Laboratories, Inc., Cambridge, MA (US);

Inventors:

Toshiaki Koike-Akino, Boston, MA (US);

Ye Wang, Boston, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/45 (2006.01); H03M 13/13 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
H03M 13/458 (2013.01); G06F 13/4027 (2013.01); G06F 13/4282 (2013.01); H03M 13/13 (2013.01); H03M 13/616 (2013.01);
Abstract

Data communications and storage systems require error control techniques to be transferred successfully without failure. Polar coding has been used as a state-of-the-art forward error correction code for such an error control technique. However, the conventional decoding based on successive cancellation has a drawback in its poor performance and long latency to complete. Because the factor graph of polar codes has a lot of short cycles, a parallelizable belief propagation decoding also does not perform well. The method and system of the present invention provide a way to resolve the issues by introducing a protograph lifting expansion for a polar coding family so that highly parallelizable decoding is realized to achieve a high coding gain and high throughput without increasing the computational complexity and latency. The invention enables an iterative message passing to work properly by eliminating short cycles through a hill-climbing optimization of frozen bits allocation and permutation.


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