The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Sep. 30, 2021
Applicant:

Zhejiang University, Hangzhou, CN;

Inventors:

Zhiwei Xu, Hangzhou, CN;

Jiangbo Chen, Hangzhou, CN;

Jiabing Liu, Hangzhou, CN;

Hui Nie, Hangzhou, CN;

Kaijie Ding, Hangzhou, CN;

Chunyi Song, Hangzhou, CN;

Assignee:

ZHEJIANG UNIVERSITY, Hangzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/18 (2006.01); H03L 7/089 (2006.01); H03L 7/099 (2006.01); H04B 1/40 (2015.01);
U.S. Cl.
CPC ...
H03L 7/18 (2013.01); H03L 7/0891 (2013.01); H03L 7/099 (2013.01); H04B 1/40 (2013.01);
Abstract

Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.


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