The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Apr. 10, 2020
Applicant:

Lumentum Japan, Inc., Kanagawa, JP;

Inventors:

Shigenori Hayakawa, Tokyo, JP;

Hironori Sakamoto, Kanagawa, JP;

Shunya Yamauchi, Kanagawa, JP;

Yoshihiro Nakai, Kanagawa, JP;

Assignee:

Lumentum Japan, Inc., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/22 (2006.01); H01S 5/343 (2006.01); H01S 5/026 (2006.01); H01S 5/227 (2006.01); H01S 5/042 (2006.01); H01S 5/125 (2006.01);
U.S. Cl.
CPC ...
H01S 5/2224 (2013.01); H01S 5/0265 (2013.01); H01S 5/04256 (2019.08); H01S 5/2226 (2013.01); H01S 5/2227 (2013.01); H01S 5/2275 (2013.01); H01S 5/3434 (2013.01); H01S 5/125 (2013.01);
Abstract

A buried semiconductor optical device comprises a semiconductor substrate; a mesa-stripe portion including a multi-quantum well layer on the semiconductor substrate; a buried layer consisting of a first portion and a second portion, the first portion covering one side of the mesa-stripe portion, the second portion covering the other side of the mesa-stripe portion, and the first portion and the second portion covering a surface of the semiconductor substrate; and an electrode configured to cause an electric current to flow through the mesa-stripe portion, the buried layer comprising, from the surface, a first, second, and third sublayer, the first and third sublayer each consisting of semi-insulating InP, the first sublayer and the second sublayer forming a pair structure, the second sublayer being located above the multi-quantum well layer, and the second sublayer consisting of one or more layers selected from InGaAs, InAlAs, InGaAlAs, InGaAsP, and InAlAsP.


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