The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Nov. 30, 2020
Applicant:

Tohoku-microtec Co., Ltd., Sendai, JP;

Inventor:

Makoto Motoyoshi, Sendai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/62 (2010.01); H01L 23/00 (2006.01); H01L 25/075 (2006.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 25/0753 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13157 (2013.01); H01L 2224/13163 (2013.01); H01L 2224/13166 (2013.01); H01L 2224/13171 (2013.01); H01L 2224/13178 (2013.01); H01L 2224/13184 (2013.01); H01L 2224/13187 (2013.01); H01L 2224/16013 (2013.01); H01L 2224/16238 (2013.01);
Abstract

A stacked semiconductor device encompasses a mother-plate having a mounting-main surface and a bottom-main surface, an onboard-element having a connection face facing to the mounting-main surface, a parent bump provided on the mother-plate, having a mother-site wall made of a layer of conductor, mother-site wall is perpendicular to the mounting-main surface, and a repair bump provided on the onboard-element at a side of the connection face, having a repair-site wall made of a layer of conductor having different hardness from the mother-site wall, the repair-site wall is perpendicular to the connection face, configure to bite each other with the parent bump at an intersection between the mother-site wall and the repair-site wall conductor.


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