The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Apr. 05, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junghwan Huh, Suwon-si, KR;

Dongchan Kim, Suwon-si, KR;

Dae Hyun Kim, Suwon-si, KR;

Euiju Kim, Suwon-si, KR;

Jisoo Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 29/42364 (2013.01); H01L 29/4916 (2013.01); H01L 29/518 (2013.01); H01L 29/7827 (2013.01);
Abstract

A semiconductor device includes a substrate including an active region, a gate trench disposed in the substrate and crossing the active region; a gate dielectric layer disposed in the gate trench; a first gate electrode disposed on the gate dielectric layer and including center and edge portions; a second gate electrode disposed on the first gate electrode; a gate capping insulating layer disposed on the second gate electrode and filling the gate trench; and first and second impurity regions disposed in the substrate opposite to each other with respect to the gate trench. A top surface of each of the center and edge portions contacts a bottom surface of the second gate electrode. The top surface of the second gate electrode is concave. The bottom surface of the gate capping insulating layer is convex, and a side surface of the gate capping insulating layer contacts the gate dielectric layer.


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