The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

May. 23, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Joseph Maurice Khayat, Bedford, NH (US);

Marco Corsi, Oak Point, TX (US);

Lemuel Herbert Thompson, Melissa, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H03K 19/0185 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H03K 17/06 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1045 (2013.01); H01L 29/402 (2013.01); H01L 29/7816 (2013.01); H03K 17/063 (2013.01); H03K 19/018507 (2013.01); H01L 29/0653 (2013.01); H01L 29/42368 (2013.01);
Abstract

In the described examples, a driver includes a signal controller that provides a gate control signal to a gate buffer coupled to a gate of a transistor and a field plate control signal to a field plate buffer coupled to a field plate of the transistor. The signal controller provides a rising edge on the field plate control signal causing the field plate buffer to provide a bias voltage on the field plate of the transistor a predetermined amount of time after providing a rising edge on the gate control signal that causes the gate buffer to provide a turn-on voltage on the gate of the transistor that causes the transistor to transition from a cutoff region to a saturation region and to a linear region.


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